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The C0-microSD Operational Model

The C0-microSD operates as a UxHw coprocessor. The host offloads computation to the module over the SD interface, the module executes it on the built-in Signaloid SoC, and the host reads back results through the shared Memory-Mapped Input/Output (MMIO) interfacing model.

Coprocessor lifecycle​

Working with the C0-microSD follows a four-step lifecycle:

  1. Flash the application. Build your application for the Signaloid SoC and flash it to the module's non-volatile memory while the module is in Bootloader mode. At reset, the SoC copies the first 128 KiB of the user-data region into its RAM and executes it. See Developing RISC-V Applications and Flash the C0-microSD.
  2. Start the application. Switch the module to Signaloid SoC mode and power-cycle it; the SoC then begins executing your application. See Switch Between Operation Modes.
  3. Exchange data. The host and the device application communicate through the MMIO command and status registers and the Manager-Out, Subordinate-In (MOSI) and Manager-In, Subordinate-Out (MISO) data buffers: the host writes operands and a command, the device computes, and the host reads back results. See Host Interface and Protocol.
  4. Return to Bootloader mode when you want to flash a new application: switch modes and power-cycle the module again.

The application running on the SoC can use a subset of Signaloid's UxHw distribution-extended computation, so that the input distributions propagate to the outputs automatically.

The lifecycle restarts at step 2 whenever the module loses power. The module reloads your application from the flash and runs it again on its own, so the host needs to do nothing, but the application begins from the start and keeps nothing that it held in memory. See Power Cycles and State.

Beyond the coprocessor model​

The coprocessor lifecycle above uses two of the module's operating modes: Bootloader and Signaloid SoC. The C0-microSD also supports custom user bitstreams and doubles as an open FPGA development board. See Modes and Custom Bitstream for the full mode model, and Custom FPGA Design for the FPGA workflows.

Next steps​

  • MMIO Interfacing Model, the registers, buffers, and handshake that carry each step of the lifecycle.
  • SD Interface, the physical link that every one of those steps travels over.
  • Getting Started, the same lifecycle in practice, from a new module to a running application.
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