| UxHw | Signaloid's distribution-extended computation model, realized in silicon on the compute modules and in the Signaloid Cloud Compute Engine (SCCE). |
| Signaloid SoC | The canonical name for the core compute IP that runs on a module in its coprocessor mode. |
| MMIO interfacing model | The shared memory-mapped I/O model through which a host communicates with any module. |
| Compute module | A Signaloid hardware product that runs the Signaloid SoC as a UxHw coprocessor (C0-microSD, C0-microSD+). |
| Operational mode | A distinct behavior of a module. Every module is single-mode except the C0-microSD. |
| Bootloader mode | A C0-microSD-only mode used to program the device. |
| Custom user bitstream | A user-authored FPGA bitstream, supported only on the C0-microSD. |
| Warmboot | The iCE40 FPGA capability the C0-microSD bootloader uses to reconfigure the FPGA from one of several stored images at power-up. |
| MOSI / MISO buffer | Shared MMIO data buffers for host→device (MOSI) and device→host (MISO) bulk transfer. |
| XIP | Execute-in-place: running code directly from SPI flash instead of copying it into RAM first (a C0-microSD+ execution mode, selected at build time with MODE := xip). |
| Sector | The 4 KiB unit in which the SPI flash of a compute module erases. Writing to a sector erases all 4 KiB of it, so a write replaces the whole sector rather than only the bytes you supply. |
| Power cycle | Removing power from a module and restoring it. Every register returns to its default value and the module loses the contents of every memory, while the data held in the SPI flash survives. |
| Athens-8 / Athens-16 | UxHw distributional representation precision. Larger representation precision leads to more accurate distributional representations at the cost of fewer in-flight distributions. |
| iCE40 / CrossLink-NX | Lattice FPGA families used as the compute substrate of, respectively, the C0-microSD and the C0-microSD+. |