C0-microSD+ Benchmarks
This page describes how Signaloid measures the performance of the C0-microSD+ and reports the resulting figures.
Benchmark methodology
The benchmarks evaluate the speedup you gain by replacing Monte Carlo simulation of sensor calibration and conversion routines with UxHw-based computation running on the C0-microSD+. Each benchmark application exists as two builds. One build runs as a multi-iteration Monte Carlo application on a reference microcontroller, and the other build runs as a UxHw application on the Signaloid SoC of the C0-microSD+.
The reference platform is an ARM Cortex-M33 microcontroller running at 150 MHz. The UxHw builds use the Athens-16 representation.
The two builds are comparable only when they produce results of equal quality. Signaloid therefore chooses the UxHw representation so that the output probability distribution reaches the same degree of convergence as the Monte Carlo result. The reported speedup is the ratio of the two latencies.
The application kernels in the table below are the manufacturer-specified calibration algorithms that convert each measured ADC value into a calibrated and usable sensor output.
Latency figures cover the compute kernel on each platform. They do not include the host-side block read and write transactions that carry operands and results across the SD interface. For those figures, see Specifications.
For the application sources that Signaloid uses as benchmark kernels, see Examples and Demos.
Results
The figures below come from revision 0.2 of the C0-microSD+ datasheet, which Signaloid marks as preliminary.
| Application | Monte Carlo iterations | Monte Carlo latency | UxHw latency | UxHw speedup |
|---|---|---|---|---|
| FLIR Ax5 | 36k | 1.6 s | 91.52 ms | 18× |
| Flusso FLS110 | 291k | 3 s | 18.67 ms | 162× |
| NXP MPX4100A | 185k | 0.7 s | 4.65 ms | 154× |
| NXP MPXx6250A | 215k | 0.8 s | 4.61 ms | 181× |
| Sensirion SDP3x | 193k | 2.3 s | 48.13 ms | 49× |
| Sensirion SFM3100 | 2.7M | 8.2 s | 1.18 ms | 6990× |
| Sensirion SHT3xARP | 193k | 1.6 s | 12.93 ms | 129× |
| Sensirion SHT4xI | 204k | 1.7 s | 12.84 ms | 138× |
| TI TMCS112x | 10k | 34.88 ms | 4.53 ms | 7.6× |
UxHw latency is the latency for achieving the same degree of convergence of the distributional result as the multi-iteration Monte Carlo.
Next steps
- UxHw in Silicon, why distributional execution replaces the Monte Carlo iterations counted above.
- Specifications, the compute, memory, and power figures behind these results.
- Developing UxHw Applications, running your own workload on the module.
- Examples and Demos, the demo applications these measurements come from.