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The C0-microSD+ Operational Model

The C0-microSD+ operates as a UxHw coprocessor. The host offloads computation to the module over the SD interface, the module executes it on the built-in Signaloid SoC, and the host reads back results through the MMIO Interfacing Model.

The module features the Signaloid SoC, and the coprocessor lifecycle described below is how you put it to work.

Coprocessor lifecycle​

Working with the C0-microSD+ follows a four-step lifecycle.

  1. Flash the application. Build your device application for the Signaloid SoC and flash it to the user data region of the SPI flash. See Developing UxHw Applications and Flash an application.
  2. Start the core. The host releases the RISC-V core from reset by setting bit 0 (rstn) of the CONFIG register, which the host toolkit exposes as the config core-start action. The core then begins executing your application. See Start and stop the core.
  3. Exchange data. The host and the device application communicate through the COMMAND and STATUS registers and the MMIO buffer. The host writes operands into the input half of the buffer and an operation code into COMMAND, the device computes and writes results into the output half, and the host polls STATUS and reads the results back. See Host Interface and Protocol.
  4. Stop the core. Clear bit 0 of the CONFIG register with the config core-stop action once the workload is complete. Stop the core before you flash a new application, then start it again to run the new binary.

The application running on the SoC can use a subset of Signaloid's UxHw in Silicon, so that the input distributions propagate to the outputs automatically.

Everything happens over the SD interface​

Flashing the application, starting the core, exchanging data, and stopping the core all happen through ordinary block reads and writes over the SD interface, while the module stays in its slot.

For the full development workflow, from building an application to driving it from a host, see the Develop section. For the register-level details of the handshake between the host and the device application, see Host Interface and Protocol.

Next steps​

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