The MMIO Interfacing Model

The C0-microSD+ uses a Memory-Mapped Input/Output (MMIO) interfacing model. A host communicates with the module by reading and writing a set of memory-mapped regions. This page describes the model. The concrete register addresses, the register bit assignments, and the full memory map are reference tables in Host Interface and Protocol.

Region types

The C0-microSD+ exposes three kinds of memory-mapped region.

• Control and configuration registers, through which the host configures the module and issues requests. The canonical example is the COMMAND register, which the host writes to request an operation. The CONFIG register carries the core reset, LED, and debug pin controls, and a separate key register controls whether the bitstream region of the SPI flash accepts writes.
• Status registers, through which the device application reports its progress and the status of its results. The canonical example is the STATUS register, which the host polls.
• Data buffers, through which bulk operands and results move. Input data travels through the MOSI (host to device) half of the MMIO buffer, and output data travels through the MISO (device to host) half.

Request/response handshake

The host and the device application interact through a polled request and response handshake.

1. The host writes operands into the input half of the MMIO buffer.
2. The host writes an operation code to the COMMAND register.
3. The device application, running on the Signaloid SoC, observes the command, sets STATUS to calculating, and performs the operation.
4. On completion the device application writes its results into the output half of the MMIO buffer and sets STATUS to done.
5. The host polls STATUS, reads the results, and then clears COMMAND to acknowledge. The device application returns to waiting for command.

The Signaloid device-side headers define four conventional status values.

Value	Name	Meaning
0	kSignaloidSoCStatusWaitingForCommand	Idle and ready to accept a new command.
1	kSignaloidSoCStatusCalculating	Processing the requested command.
2	kSignaloidSoCStatusDone	A result is available in the output buffer.
3	kSignaloidSoCStatusInvalidCommand	The requested command was not recognized.

These four values are a convention rather than a requirement. Both COMMAND and STATUS are plain 32-bit registers, so your application is free to define its own command codes and its own status values.

One unified address space

The C0-microSD+ has one unified address space. The host and the device application address the same registers and the same buffers at the same addresses. There are no separate block offsets for the host, and there is no host view of the memory map that differs from the view the device application sees.

This is the most important way in which the C0-microSD+ differs from other memory-mapped compute modules, which expose one set of addresses to the software running on the device and a second, separate set of block offsets to the host.

For example, the device application reads COMMAND at address 0x08200000, and the host reaches that same register by seeking to 0x08200000 on the block device. The same holds for STATUS, for CONFIG, and for every byte of the MMIO buffer. You never translate between two addressing views, and you never need an address translation table.

The MMIO buffer

The C0-microSD+ provides a single 64 KiB MMIO buffer based at 0x08300000. The buffer is split down the middle into two halves of 32 KiB each.

Half	Direction	Base address	Size
Output (MISO)	Device to host	0x08300000	32 KiB
Input (MOSI)	Host to device	0x08308000	32 KiB

The host writes operands into the input half and reads results back from the output half. The device application does the reverse, reading its operands from the input half and writing its results into the output half. The device-side C API exposes each half as a set of typed arrays, for example kC0HALInputBufferFloat and kC0HALOutputBufferFloat, each with a matching length constant.

How the SD interface carries MMIO

The physical link is the SD Interface. MMIO transactions are carried by ordinary block read and write operations addressed to positions in the unified address space, so any host that can access an SD block device can drive the module.

For the complete register table, the CSR addresses, the CONFIG bit assignments, and the flash layout, see Host Interface and Protocol.

Next steps

• SD Interface, the block reads and writes that carry these transactions.
• Using the Hardware Abstraction Layer, the C library that reaches these registers and buffers from the device application.
• Using the Python Host Interface, the package that reaches them from the host.